1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to an apparatus and method for locking out a source synchronous strobe receiver to preclude erroneous indications resulting from bus noise in a microprocessor system that employs source synchronous data and address buses.
2. Description of the Related Art
A present day computer system employs a source synchronous system bus to provide for exchange of data between bus agents, such as between a microprocessor and a memory hub. A “source synchronous” bus protocol allows for the transfer of data at very high bus speeds. Source synchronous protocols operate on the principle that a transmitting bus agent places data out on the bus for a fixed time period and asserts a “strobe” signal corresponding to the data to indicate to a receiving bus agent that the data is valid. Both data signals and their corresponding strobe are routed over the bus by the same propagation path, thus enabling a receiver to be relatively certain that when transition of the corresponding strobe is detected, data is valid on the data signals.
But data strobes are subject to error resulting from a number of sources including, but not limited to, conducted and radiated emissions from other signals in close proximity. And whereas former bus protocols provided sampling mechanisms to detect and correct errors on the bus, errors due to data strobe glitches on a source synchronous bus are considered more complex because there is no absolute time reference, such as was provided for in former bus protocols by a number of bus clock cycles, that can be relied upon to determine if a transition on a strobe signal is a real transition or a glitch. In present day source synchronous buses, several bursts of data are transmitted during a single bus clock cycle, and the only indication provided to a receiving bus agent that data is valid is the data strobe itself. The timing of strobe transitions is a function of the bus clock frequency, but at a receiver the switching of a data strobe seems, for all intents and purposes, to be asynchronous to the bus clock. This is because there is a fixed, but unknown, phase difference between the bus clock and the data strobes.
Consequently, a number of techniques have been provided to detect and correct glitches that occur in the strobes over source synchronous buses. One class of techniques for is of interest in the present application, that is, so-called “receiver lockout” techniques. As noted above, source synchronous bus protocols often specify a fraction of a bus clock cycle for strobing of data. Consider the specific case where a data strobe cycle is constrained to be ¼ of a bus clock cycle. Extant techniques provide a number of mechanisms to lock out a receiver for a period of time equal to ¼ cycle of the bus clock. But these techniques employ fixed logic, typically a string of inventers, to calculate the lockout time and, consequently, when operating parameters change, such as slight variations in bus clock frequency, variations in device temperature, and variations in core operating voltage, lockout time is adversely affected. In addition, fabrication process variations can cause lockout time to vary from part to part. Thus, designers are forced to employ worst-case scenarios to employ these techniques.
The present inventors have noted that conventional receiver lockout techniques are deficient because they do not provide any compensation for the above noted variations, and thus a substandard mechanism is provided through which error is introduced into a computer system design.
Accordingly, what is needed are apparatus and methods that enable a receiving device to lock out reception of a period of time following valid detection of a source synchronous strobe, where the period of time is continually updated to account for variations in bus and core voltages, temperature, and changes in bus clock frequency.
What is also needed are techniques for source synchronous strobe lockout that provide compensation for variations in fabrication processes, at the lot, wafer, and cross-die levels.